The finish line circuit below detects the initial of three vehicles to cross the line and illuminates a 25 watt 120 VAC lamp indicating the winning lane. Three photo transistors are utilized which can be incorporated into the track with a light shining downwards onto the finish line so that as the car passes over the sensor, the light is blocked, activating the relay and lighting the lamp for the appropriate lane. The light source should be an incandescent type; fluorescent lights may not operate effectively due to low infrared content. The circuit was tested using a 100 watt incandescent light fixture approximately 3 feet above the photo transistors.
The photo transistors are connected such that a logic low (0 volts) normally appears at the input to a NAND gate and as a vehicle crosses the line obstructing light to the transistor, the logic level will shift high (+6 volts). The resulting logic low level from the output of the gate (3 input NAND) is fed to a SET/RESET latch constructed from two dual input NAND gates (1/2 of a 74HC00) the (logic high) output of which controls the MPS2222A buffer transistor and solid state relay. The inverted output of the latch (logic low) is connected back to the remaining two (3 input NAND gate) inputs locking them out. Two extra 74HC00 gates are not utilized and should have their inputs (pins 9,10,12,13) grounded to avoid possible oscillation. The circuit is reset with a momentary push button linked to the reset side of each latch. The reset button may need to be pressed after initial power application. Components for the circuit may be obtained from Radio Shack; however, the RSU numbers may require special ordering or procurement from another source. The 74HC00 and 74HC10 are CMOS parts and should be handled carefully to avoid potential damage from static electricity. It may be advantageous to use IC sockets to facilitate wiring completion prior to IC insertion into the sockets. One can briefly touch a grounded surface (computer chassis or other metal grounded surface) just before handling CMOS circuits to reduce the possibility of damage from static electricity.